1. Technical Field
The present invention relates to a D-A conversion apparatus and an A-D conversion apparatus. More particularly, the present invention relates to a D-A conversion apparatus that outputs an analog output voltage according to digital input data and to an A-D conversion apparatus provided with the D-A conversion apparatus.
2. Related Art
A charge redistribution A-D conversion apparatus is known as in, for example, US Unexamined Patent Application Publication US2007/0132626. The A-D conversion apparatus described in the above publication is provided with a capacitance array main D-A converter, a capacitance array correction D-A converter, a comparator, and a control logic.
The main D-A converter outputs an analog voltage according to data supplied from the control logic. The correction D-A converter is supplied with data expressing a resolution of the main D-A converter that is less than 1 LSB from the control logic and outputs an analog voltage according to the supplied data. The comparator compares an input voltage to a sum voltage obtained by adding the voltage output from the main D-A converter to the voltage output from the correction D-A converter.
The control logic changes the data supplied to the main D-A converter and the correction D-A converter in order to search for data through which the input voltage and the sum voltage are identical. The control logic then outputs the data through which the input voltage and the sum voltage are identical to an external section.
Here, the control logic supplies data that is corrected according to DNL (Differential Non Linearity) of the main D-A converter to the main D-A converter and the correction D-A converter. More specifically, the control logic supplies integer portions of the data corrected according to the DNL to the main D-A converter. Furthermore, the control logic supplies fractional portions of the data corrected according to the DNL to the correction D-A converter. Therefore, the A-D conversion apparatus described in US Unexamined Patent Application Publication US2007/0132626 can output voltage corrected by the DNL with a degree of precision less than 1 LSB.
The capacitance array D-A converter that outputs a voltage having a resolution less than 1 LSB (for example, 0.5 LSB, 0.25 LSB, . . . ) has a capacitor with a minimum unit capacitance smaller than that of a capacitor of a D-A converter that outputs a voltage having a resolution greater than or equal to 1 LSB. However, because the minimum capacitance of a capacitor that can be manufactured on a semiconductor is determined by a manufacturing process of the semiconductor, the capacitance array D-A converter that outputs a voltage having a resolution less than 1 LSB has an enlarged synthetic capacitance, which results in a lowered band. Accordingly, it is desirable that the capacitance array D-A converter have a capacitor with a larger minimum unit capacitance.
Furthermore, in a case where the voltage corrected by the DNL is output from the D-A converter, it is necessary that a measurement device be connected to the D-A converter from the outside to measure the DNL in advance, and the correction data according to a measurement result must be written onto an internal memory of the D-A converter. Accordingly, it is difficult for the D-A converter to easily adjust the correction data.